Stacked local interconnect structure and method of fabricating same

ABSTRACT

A method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of application Ser. No. 09/710,399,filed Nov. 9, 2000, now U.S. Pat. No. 6,498,088, issued Dec. 24, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to local interconnect structures includedin integrated circuit semiconductor devices. Specifically, the presentinvention relates to a method of forming stacked local interconnects aswell as a method of using local interconnect structures to protectunderlying device features from shooting during fabrication of anintegrated circuit semiconductor device.

2. State of the Art

Higher performance and decreased size of integrated circuit (“IC”)semiconductor devices are constant goals of the semiconductor industry.Both goals are generally achieved by decreasing feature dimensions whileincreasing the density with which the electrical components that formthe semiconductor devices are packaged. As is well known, state of theart semiconductor devices, such as static random-access memory (SRAM)devices and logic circuits, include device features well below 0.25 μmin size and make use of multiple metallization levels as well as localinterconnects in order to achieve desired packaging densities.

Local interconnects are often used to electrically connect localizedelectrical features, such as transistors or other circuit components,formed at a given level within a semiconductor device. Use of localinterconnects greatly reduces the area necessary to form a given numberof electrical features within a semiconductor device, thereby reducingthe total size of the semiconductor device itself. However, as is alsowell known, it is often desirable to electrically connect two or moreelectrical features which are isolated within a given level of amultilevel semiconductor device. As used herein, the term “isolated”identifies electrical features which are remotely located within asingle level, separated by one or more unrelated electrical featuresincluded in the same level, or both remotely located and separated byone or more unrelated electrical features. In order to electricallyconnect such isolated electrical features, multilevel interconnectstructures, which include one or more metallization layers formed athigher levels within a semiconductor device, and the isolated electricalfeatures are electrically connected via a multilevel interconnectstructure by extending contact plugs up from the isolated features tothe metallization layers included in the multilevel interconnectstructure. Because they extend up into higher levels within multilevelsemiconductor devices, multilevel interconnect structures allowconnection of isolated electronic features using complex interconnectstructures without shooting to any unrelated electrical features thatmay exist between the isolated features being electrically connected.

Electrically connecting isolated electrical features using multilevelinterconnects, however, has significant disadvantages. For example,forming multilevel interconnects at higher elevations within asemiconductor device complicates the design of higher levels occupied bythe multilevel interconnect structures, thereby reducing designflexibility at the higher levels and, ultimately, increasing the size ofthe finally formed semiconductor device. Moreover, the methods used tofabricate multilevel interconnects are relatively complicated andgenerally require the use of enlarged contact pads in order tocompensate for fabrication errors, which may occur during the masking oretching steps used to form the contact plugs necessary to electricallyconnect the isolated electrical features via the multilevelinterconnect.

Therefore, a method of electrically connecting isolated electricalfeatures included within the same level of a multilevel semiconductordevice, which does not require the formation of multilevel interconnectstructures but which protects any intervening, unrelated semiconductordevice features, would be advantageous. Such a method would minimize theintrusion of multilevel interconnect structures into higher levelswithin a multilevel semiconductor device, which, in turn, would increasethe area available within such higher layers for fabrication of furtherelectrical features and greatly enhance the design flexibility of stateof the art semiconductor devices.

SUMMARY OF THE INVENTION

The present invention addresses the foregoing needs by providing amethod of forming stacked local interconnects which electrically connectisolated electrical features included within a single level of amultilevel semiconductor device without occupying space at higher levelswithin the multilevel semiconductor device. In a first embodiment, themethod of the present invention provides a stacked local interconnectwhich electrically connects a first group of interconnected electricalfeatures with one or more additional isolated groups of interconnectedelectrical features or one or more isolated individual electricalfeatures. In a second embodiment, the method of the present inventionprovides a stacked local interconnect which electrically connects anindividual electrical feature to one or more additional isolatedelectrical features. Significantly, in each of its embodiments, themethod of the present invention does not require formation of contactplugs, and, therefore, obviates the disadvantages associated withcontact plug formation. Moreover, portions of the stacked localinterconnect structures formed in each embodiment of the method of thepresent invention not only serve to electrically connect isolated devicefeatures but also serve to protect underlying, unrelated semiconductordevice features from damage during subsequent etch steps. Therefore, thepresent invention also includes a method for protecting semiconductordevice features from damage due to inadvertent etching of such features.

Other features and advantages of the present invention will becomeapparent to those of skill in the art through a consideration of theensuing description, the accompanying drawings, and the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The figures presented in conjunction with this description are notactual views of any particular portion of an actual IC device orcomponent but are merely representations employed to more clearly andfully depict the present invention.

FIG. 1 through FIG. 15 provide schematic illustrations of semiconductordevice structures formed while carrying out various steps of the firstembodiment of the method of the present invention.

FIG. 16 through FIG. 30 provide schematic illustrations of semiconductordevice structures formed while carrying out various steps of the secondembodiment of the method of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In a first embodiment, the method of the present invention enables theformation of stacked local interconnects facilitating the electricalconnection of a first set of interconnected electrical features to asecond set of interconnected electrical features. Significantly, thestacked local interconnects are formed within a single level of amultilevel semiconductor device, thereby simplifying device levelsoverlying the level occupied by the electrical features which areinterconnected by the stacked local interconnects.

To carry out the first embodiment of the method of the presentinvention, a first intermediate semiconductor device structure 10 isprovided. As is illustrated in drawing FIG. 1, the first intermediatesemiconductor device structure 10 includes a semiconductor substrate 11having desired features, such as transistors 12 a, 12 b, source anddrain regions 14 a-14 d, isolation regions 15 a-15 c, or otherelectrical features or components, already formed thereon. As usedherein, the term “semiconductor substrate” signifies any constructionincluding semiconductive material, including, but not limited to, bulksemiconductive material, such as a semiconductive wafer, either alone orin assemblies including other materials, and semiconductive materiallayers, either alone or in assemblies including other materials.Moreover, in order to ease description of the first embodiment of thepresent invention, drawing FIG. 1 provides a greatly simplifiedillustration of a typical first intermediate semiconductor devicestructure 10. It is well known in the art that an intermediatesemiconductor device structure may further include other featuresnecessary for the proper function of the completed semiconductor device,and, as will be easily appreciated from the description provided herein,application of the first embodiment of the method of the presentinvention is not limited to the simplified schematic representationsprovided in the accompanying figures.

As is shown in drawing FIG. 2, an etch stop layer 16 is formed over thefirst intermediate semiconductor device structure 10. The etch stoplayer 16 may include any suitable material, such as silicon dioxide(SiO₂), silicon oxynitride (Si_(x)O_(y)N₂), tetraethylorthosilicate(TEOS), or silicon nitride (Si₃N₄). Further, the etch stop layer may beformed by any well-known means, such as a chemical vapor deposition(CVD) process. Preferably, the etch stop layer 16 includes a layer ofSi_(x)O_(y)N₂ deposited by a plasma-enhanced CVD process. The etch stoplayer 16 protects the various features included on the semiconductorsubstrate 11, such as the transistors 12 a, 12 b, from degradation ordamage during subsequent etch steps used to define desired localinterconnects. Moreover, the etch stop layer 16 may additionally serveas a barrier layer, substantially preventing diffusion of contaminantsfrom overlying material layers into the semiconductor substrate 11 orany features included on the semiconductor substrate 11.

After formation of the etch stop layer 16, a passivation layer 18 and aninterlayer dielectric (ILD) 20 are formed over the etch stop layer 16(shown in drawing FIG. 3). The passivation layer 18 may be composed ofknown silica materials, such as SiO₂, borophosphosilicate glass (BPSG),phosphosilicate glass (PSG), borosilicate glass (BSG), or doped orundoped oxide materials. BPSG is the presently preferred passivationmaterial, and where BPSG is used, the passivation layer 18 may be formedby depositing a layer of BPSG and utilizing known reflow or polishingtechniques to achieve a passivation layer 18 having a desired thicknessand planarity. The ILD 20 may include any suitable dielectric material,such as SiO₂, Si_(x)O_(y)N₂, or, preferably, Si₃N₄. Again, the ILDmaterial may be formed by any known process, such as known CVDprocesses.

As can be seen in drawing FIG. 4, after formation of the passivationlayer 18 and the ILD 20, a first resist 22 is formed over the ILD 20.Any desirable resist material may be used to form the first resist 22,and, as can also be appreciated from drawing FIG. 4, the first resist 22is exposed and developed according to well-known processes to define apattern corresponding in size, shape, and location to a desired firstlocal interconnect.

Using the pattern defined in the first resist 22, the ILD 20 is etchedto define a trench 24 into the ILD 20. The trench 24 will enclose anddefine the first local interconnect. Though any suitable etch processmay be used, a dry plasma etch process is preferred. Because it isdifficult to precisely control the depth of the ILD 20 etch, it islikely that the trench 24 will extend at least slightly into thepassivation layer 18, as is shown in drawing FIG. 5. After formation ofthe trench 24, the first resist 22 is stripped using means known in theart.

The trench 24 is then filled with a desired conductive material. As isillustrated in drawing FIG. 6, in order to fill the trench 24, a layerof conductive material 26, such as tungsten, is formed over the trench24 and the remaining portions of the ILD 20 by known means, such as asputter deposition or CVD process. The layer of conductive materiallayer 26 is then polished as known in the art, such as by a chemicalmechanical planarization (CMP) process, to achieve a first localinterconnect 28, which extends through the ILD 20 but is substantiallycoplanar with the top surface 30 of the ILD 20 (shown in drawing FIG.7).

Optionally, where desirable, the trench 24 defining the firstinterconnect may be filled by first depositing a barrier layer 32 overthe trench 24 and remaining portion of the ILD 20. The barrier layer 32may include a first conductive material, such as titanium, tungsten,tantalum, titanium nitride, tungsten nitride, or tantalum nitride, andthe barrier layer is formed by well-known means in the art. As can beseen in drawing FIG. 8, the barrier layer 32 partially fills the trench24. After formation of the barrier layer 32, a second conductive layer34 is formed over the barrier layer 32. The second conductive layer 34may include any suitable material, such as tungsten, and can also beformed using well-known techniques. The barrier layer 32 and the secondconductive layer 34 are then polished by suitable means, such as a knownCMP process, to again achieve a first local interconnect 28, whichextends through the ILD 20 but is substantially coplanar with the topsurface 30 of the ILD 20 (shown in drawing FIG. 9).

Regardless of whether the first local interconnect 28 is formed using abarrier layer 32 and a second conductive layer 34 or simply a singlelayer of conductive material 26, the first local interconnect 28 can besized, shaped, and positioned as desired. Preferably, however, the localinterconnect is sized, shaped, and positioned such that, after formationof the final stacked local interconnect structure (shown in drawing FIG.13 and drawing FIG. 15), the first local interconnect structure 28enables the electrical connection of a first group of interconnectedelectrical features (e.g., transistors 12 a and 12 b) to one or moreadditional groups of interconnected electrical features (notillustrated).

Once the first local interconnect 28 is formed, a second resist 40 isformed over the semiconductor substrate 11, as can be seen in drawingFIG. 10. As was true in regard to the first resist 22, any desirableresist material may be used to form the second resist 40. The secondresist 40 is exposed and developed according to well-known processes todefine the desired shape and location of the second and third localinterconnects, which will complete the stacked local interconnectstructure.

Using the pattern defined in the second resist 40, the ILD 20 andpassivation layer 18 are etched to define openings 42 a, 42 b using aself-aligned contact (SAC) etch, which is selective to the material(s)used in first local interconnect 28 and etch stop layer 16 (FIG. 11). Ascan be appreciated by reference to drawing FIG. 11, the openings 42 a,42 b formed by the SAC etch extend down through the passivation layer 18and expose each of the electrical features, such as transistors 12 a, 12b, which are to be electrically connected. Moreover, because the SACetch is selective to the material used to form the first localinterconnect 28, the portion 44 of the passivation layer 18 underlyingthe first local interconnect 28 remains intact, providing properisolation for each of the electrical features to be interconnected, suchas transistors 12 a and 12 b, and protecting any intervening, unrelatedelectrical features that may be included underneath the first localinterconnect 28. After openings 42 a, 42 b have been formed, the secondresist 40 is stripped using means known in the art.

In order that the second and third local interconnects may be formed inelectrical contact with the electrical features exposed by openings 42 aand 42 b, portions of the etch stop layer 16 overlying the electricalfeatures to be interconnected, such as portions 46 a and 46 b (shown indrawing FIG. 11), are selectively removed by a known etch process. Theetch process is preferably a selective plasma dry etch process, such asa “punch etch” process. Illustrated in drawing FIG. 12 is anintermediate semiconductor device structure 10 after portions 46 a, 46 bof the etch stop layer 16 have been removed by a desirable etch process.

After portions of the etch stop layer 16, such as portions 46 a and 46b, have been removed to reveal the electrical features, such astransistors 12 a and 12 b, to be electrically connected, a layer ofconductive material 48 is formed over openings 42 a, 42 b, the firstlocal interconnect 28, and the remaining portions of the ILD 20 (shownin drawing FIG. 12). The layer of conductive material 48 fills openings42 a and 42 b and may include any suitable conductive material, such astungsten, the presently preferred material. The layer of conductivematerial 48 may be formed using a known deposition process. As can beappreciated by reference to drawing FIG. 13, the layer of conductivematerial 48 is then polished as known in the art, such as by a chemicalmechanical polishing (CMP) process, to achieve second and third localinterconnects 50, 51, which extend through the ILD 20 and passivationlayer 18, are in electrical contact with the electronic features, suchas transistors 12 a and 12 b, to be interconnected, are in electricalcontact with the first local interconnect 28, and are substantiallycoplanar with the top surface 30 of the ILD 20 (shown in drawing FIG.13).

Alternatively, as shown in drawing FIG. 14 and drawing FIG. 15, thesecond and third local interconnects 50, 51 may also be formed by firstdepositing a barrier layer 52 comprised of any suitable material, suchas those materials already described in regard to first localinterconnect 28. As can be seen in drawing FIG. 14, the barrier layer 52partially fills openings 42 a and 42 b. After formation of the barrierlayer 52, a second conductive layer 54 is formed over the semiconductorsubstrate 11. The second conductive layer 54, which can be formed usingwell-known techniques, completely fills openings 42 a and 42 b and mayinclude any suitable material, such as tungsten. The barrier layer 52and the second conductive layer 54 are then polished by suitable means,such as a known CMP process, to achieve second and third localinterconnects 50, 51, which extend through the ILD 20 and passivationlayer 18, are in electrical contact with the electrical features, suchas transistors 12 a and 12 b to be interconnected, are in electricalcontact with the first local interconnect 28, and are substantiallycoplanar with the top surface 30 of the ILD 20 (shown in drawing FIG.15).

Reference to drawing FIG. 13 and drawing FIG. 15 highlights that thefirst embodiment of the method of the present invention provides astacked local interconnect structure formed of a first localinterconnect 28, a second local interconnect 50, and a third localinterconnect 51, which enables the interconnection of two or moreisolated groups of interconnected electrical features included in thesame level of a multilevel IC device. For example, as shown in drawingFIG. 13 and drawing FIG. 15, a first group of electrical features,transistors 12 a and 12 b, is electrically connected by second localinterconnect 50, a second set of electrical features (not illustrated)is electrically connected by third local interconnect 51, and the firstand second groups of electrical features are electrically connected byfirst local interconnect 28. Moreover, the stacked local interconnectsformed by the first embodiment of the present invention do not includemultilevel metallization structures that would otherwise extend into andcomplicate higher levels included in a multilevel semiconductor device.Finally, the fabrication of the stacked local interconnects isaccomplished without contact plugs and the disadvantages that accompanythe use of contact plugs, such as the need for enlarged contact pads andextra masking and etching steps. Therefore, the first embodiment of thepresent invention provides a method for forming stacked localinterconnects that facilitate the electrical connection of isolatedgroups of interconnected electrical features, but the first embodimentof the method of the present invention also substantially reduces oreliminates the disadvantages associated with known multilevelinterconnect structures.

Though the first embodiment of the method of the present invention hasbeen described herein with reference to a stacked local interconnectstructure including a first local interconnect electrically connectingsecond and third local interconnects, the first embodiment may be usedto form any desired stacked local interconnect structure. For example,instead of a first local interconnect electrically connecting two groupsof electrically connected semiconductor device features, the firstembodiment of the present invention may be used to form a first localinterconnect electrically connecting three or more groups ofelectrically connected semiconductor device features. Or, alternatively,the first embodiment of the method of the present invention may be usedto electrically connect a first group of electrically connected featuresto one or more individual electrical features. As is easily appreciatedfrom the description provided herein, the first embodiment of the methodof the present invention is extremely flexible and provides a means bywhich a group of interconnected electrical features may be electricallyconnected to any desired number of isolated interconnected electricalfeatures or individual electrical features without the need formultilevel interconnect semiconductor device structures.

A second embodiment of the method of the present invention is similar tothe first embodiment, except that it may be used to electrically connectindividual isolated electronic features. As was true in the firstembodiment of the method of the present invention, the first step in thesecond embodiment is providing an intermediate semiconductor devicestructure 59 (shown in drawing FIG. 16) including a semiconductorsubstrate 61 having desired electrical features, such as transistors 12a-12 d, source and drain regions 14 a-14 g, or any other desiredelectrical features formed thereon. Moreover, as was true in the firstembodiment of the method of the present invention, the intermediatesemiconductor device structure 59 provided may further include any otherfeatures, such as field oxide or isolation regions 15 a-15 d, that maybe necessary for the proper function of a completed IC device. DrawingFIG. 16, like FIG. 1, provides a greatly simplified illustration of atypical first intermediate semiconductor device structure 59. As will beeasily appreciated from the description provided herein, application ofthe second embodiment of the method of the present invention is notlimited to the simplified schematic representations provided in theaccompanying figures.

As is shown in drawing FIG. 17, an etch stop layer 16 is formed over thefirst intermediate semiconductor device structure 59. The etch stoplayer 16 may include any suitable material, such as silicon dioxide(Si_(x)O_(y)N₂), silicon oxynitride (Si_(x)O_(y)N₂),tetraethylorthosilicate (TEOS), or silicon nitride (Si₃N₄). Further, theetch stop layer may be formed by any well-known means, such as achemical vapor deposition (CVD) process. Preferably, the etch stop layer16 includes a layer of Si_(x)O_(y)N₂ deposited by a plasma-enhanced CVDprocess. The etch stop layer 16 protects the various features includedon the semiconductor substrate 61, such as the transistors 12 a-12 d,from degradation or damage during subsequent etch steps used to definedesired local interconnects. Moreover, the etch stop layer 16 mayadditionally serve as a barrier layer, substantially preventingdiffusion of contaminants from overlying material layers into thesemiconductor substrate 61 or any features included on the semiconductorsubstrate 61.

After formation of the etch stop layer 16, a passivation layer 18 and aninterlayer dielectric (ILD) 20 are formed over the etch stop layer 16(shown in drawing FIG. 18). The passivation layer 18 may be composed ofknown silica materials, such as SiO₂, borophosphosilicate glass (BPSG),phosphosilicate glass (PSG), borosilicate glass (BSG), or doped orundoped oxide materials. BPSG is the presently preferred passivationmaterial, and where BPSG is used, the passivation layer 18 may be formedby depositing a layer of BPSG and polishing the BPSG layer, using knownpolishing techniques, to achieve a passivation layer 18 having a desiredthickness and planarity. The ILD 20 may include any suitable dielectricmaterial, such as SiO₂, Si_(x)O_(y)N₂, or, preferably, Si₃N₄, and,again, the ILD material may be formed by any known process, such asknown CVD processes.

As can be seen in drawing FIG. 19, after formation of the passivationlayer 18 and the ILD 20, a first resist 60 is formed over the ILD 20.Any desirable resist material may be used to form the first resist 60,and, as can also be appreciated from drawing FIG. 19, the first resist60 is exposed and developed according to well-known processes to definea pattern corresponding in size, shape, and location to a first portionof the desired stacked local interconnect.

Using the pattern defined in the first resist 60, the ILD 20 is etchedto define a trench 62 into the ILD 20, which will enclose and define thefirst portion of the stacked local interconnect. Though any suitableetch process may be used, a dry plasma etch is preferred. Because it isdifficult to precisely control the depth of the ILD 20 etch, it islikely that the trench 62 will extend at least slightly into thepassivation layer 18, as is shown in drawing FIG. 20.

The trench 62 is then filled with a desired conductive material. As isillustrated in FIG. 21, in order to fill the trench 62, a layer ofconductive material 26, such as tungsten, is formed over the trench 62and the remaining portions of the ILD 20 by known means, such as asputter deposition or CVD process. The deposited conductive materiallayer 26 is then polished as known in the art, such as by a chemicalmechanical polishing (CMP) process, to achieve a first portion 64 of thestacked local interconnect, which extends through the ILD 20, but issubstantially coplanar with the top surface 30 of the ILD 20 (shown indrawing FIG. 22).

Optionally, where desirable, the trench 62 defining the firstinterconnect may be filled by first depositing a barrier layer 32 overthe trench 62 and the remaining portions of the ILD 20. The barrierlayer 32 may include a first conductive material, such as titanium,tungsten, tantalum, titanium nitride, tungsten nitride, or tantalumnitride, and the barrier layer is formed by well-known means in the art.As can be seen in drawing FIG. 23, the barrier layer 32 partially fillsthe trench 62. After formation of the barrier layer 32, a secondconductive layer 34, which completely fills the trench 62, is formedover the barrier layer 32. The second conductive layer 34 may includeany suitable material, such as tungsten, and can also be formed usingwell-known techniques. The barrier layer 32 and the second conductivelayer 34 are then polished by suitable means, such as a known CMPprocess, to again achieve a first portion 64 of a stacked localinterconnect, which extends through the ILD 20, but is substantiallycoplanar with the top surface 30 of the ILD 20 (shown in drawing FIG.24).

Regardless of whether the first local interconnect 28 is formed using abarrier layer 32 and a second conductive layer or simply a singleconductive layer 26, the first portion 64 of the stacked localinterconnect can be sized, shaped, and positioned as desired.Preferably, however, the local interconnect is sized, shaped, andpositioned such that, after formation of the final stacked localinterconnect structure (shown in drawing FIG. 30), the first portion 64of the stacked local interconnect enables the electrical interconnectionof two or more isolated electrical features, such as transistors 12 aand 12 d.

Once the first portion 64 of the stacked local interconnect is formed, asecond resist 66 is formed over the semiconductor substrate, as can beseen in drawing FIG. 25. As was true in regard to the first resist 60,any desirable resist material may be used to form the second resist 66.The second resist 66 is exposed and developed according to well-knownprocesses to define the desired shape and location of the second andthird portions of the stacked local interconnect.

Using the pattern defined in the second resist 66, the ILD 20 andpassivation layer 18 are etched to define openings 68 a, 68 b using aself-aligned contact (SAC) etch, which is selective to the material(s)used in first portion 64 of the stacked local interconnect. As can beappreciated by reference to FIG. 26, the openings 68 a, 68 b formed bythe SAC etch extend down through the passivation layer 18 and expose theelectrical features, such as transistors 12 a and 12 d that are to beelectrically connected. Moreover, because the SAC etch is selective tothe material used to form the first portion 64 of the stacked localinterconnect, the portion 70 of the passivation layer 18 underlying thefirst portion 64 of the stacked local interconnect remains intact,providing proper isolation for the electrical features and protectingany intervening, unrelated electrical features, such as transistors 12 band 12 c, that may be included underneath the first portion 64 of thestacked local interconnect.

In order that the second and third portions of the stacked localinterconnect may be formed in electrical contact with the electricalfeatures exposed by openings 68 a and 68 b, portions of the etch stoplayer 16, such as portions 72 a and 72 b, are first selectively removedby a known etch process. The etch process is preferably a selectiveplasma dry etch process, such as a “punch etch” process. Illustrated indrawing FIG. 27 is an intermediate IC structure 59 after portions 72 a,72 b of the etch stop layer have been removed by a desirable etchprocess.

After desired portions of the etch stop layer 16 have been removed toreveal the electrical features to be electrically connected, a layer ofconductive material 48 is formed over the openings 68 a, 68 b, the firstportion 64 of the stacked local interconnect and the remaining portionsof the ILD 20 (shown in drawing FIG. 27). The layer of conductivematerial 48 may include any suitable conductive material, thoughtungsten is presently preferred, and the layer of conductive material 48may be formed using known deposition processes. As can be appreciated byreference to drawing FIG. 28, the deposited layer of conductive material48 is then polished as known in the art, such as by a chemicalmechanical polishing (CMP) process, to achieve second and third portions76, 78, which extend through the ILD 20 and passivation layer 18, are inelectrical contact with the electronic features, such as transistors 12a and 12 d, to be interconnected, are in electrical contact with thefirst portion 64 of the stacked local interconnect, and aresubstantially coplanar with the top surface 30 of the ILD 20.

Alternatively, as shown in drawing FIG. 29, the second and thirdportions 76, 78 of the stacked local interconnect may also be formed byfirst depositing a barrier layer 52 comprised of any suitable material,such as those materials already described in regard to first portion 64of the stacked local interconnect. As can be seen in drawing FIG. 29,the barrier layer 52 partially fills openings 68 a and 68 b. Afterformation of the barrier layer 52, a second conductive layer 54 isformed over the barrier layer 52. The second conductive layer 54, whichcan be formed using well-known techniques, completely fills openings 68a and 68 b and may include any suitable material, such as tungsten. Thebarrier layer 52 and the second conductive layer 54 are then polished bysuitable means, such as a known CMP process, to achieve second and thirdportions 76, 78 of the stacked local interconnect, which extend throughthe ILD 20 and passivation layer 18, are in electrical contact with theelectrical features, such as transistors 12 a and 12 d, to beinterconnected, are in electrical contact with the first portion 64 ofthe local interconnect, and are substantially coplanar with the topsurface 30 of the ILD 20 (shown in drawing FIG. 30).

Reference to drawing FIG. 28 and drawing FIG. 30 highlights the secondembodiment of the method of the present invention, which provides astacked local interconnect structure 80 formed of a first portion 64, asecond portion 76, and a third portion 78. The stacked localinterconnects formed by the second embodiment of the present inventionenable the interconnection of two or more isolated electrical featuresincluded within a single level of a multilevel semiconductor device. Forexample, as shown in drawing FIG. 28 and drawing FIG. 30, a firstisolated transistor 12 a is electrically connected by the stacked localinterconnect structure 80 to a second isolated transistor 12 d.Moreover, as was true with the stacked local interconnect structuresformed in the first embodiment of the method of the present invention,the stacked local interconnects formed by the second embodiment do notinclude multilevel metallization structures, and the fabrication of thestacked local interconnects is accomplished without contact plugs andthe disadvantages that accompany the use of contact plugs. Therefore,the second embodiment of the method of the present invention provides amethod for forming stacked local interconnects that facilitates theelectrical connection of isolated electrical features, whilesubstantially reducing or eliminating the disadvantages associated withknown multilevel interconnect structures.

Though the second embodiment of the method of the present invention hasbeen described herein in relation to a stacked local interconnectstructure including three portions electrically connecting two isolatedelectrical features, the second embodiment of the method of the presentinvention is extremely flexible and may be used to electrically connectany desired number of isolated electrical features.

Both the first and the second embodiments of the method of the presentinvention accomplish the interconnection of isolated electrical featureswithout disturbing any unrelated, intervening semiconductor devicefeatures. Moreover, the first interconnect formed in the firstembodiment and the first portion of the stacked local interconnectformed in the second embodiment protect underlying semiconductor devicefeatures from possible damage due to loss of selectivity duringsubsequent etch steps or due to misalignment of masks used to create theopenings used for the second and third interconnects in the firstembodiment as well as the second and third portions of the stacked localinterconnect of the second embodiment.

Because the SAC etch employed to created such openings is selective tothe materials used to form the first local interconnect of the firstembodiment or the first portion of the stacked local interconnect of thesecond embodiment, those features underlying the first localinterconnect or first portion of the stacked local interconnect will beprotected from damage during the SAC etch, even if the patterned masksused in the SAC step are misaligned or out of position. Therefore, wheredesired, the first local interconnect of the first embodiment of themethod of the present invention or the first portion of the stackedlocal interconnect of the second embodiment of the method of the presentinvention may be shaped and positioned to specifically protectunderlying semiconductor device features from subsequent fabricationsteps. Moreover, even where there is no need for a local interconnect ora stacked local interconnect, a protective overlying metallizationlayer, such as the first local interconnect of the first embodiment orthe first portion of the stacked local interconnect of the secondembodiment, may be formed over semiconductor device features to beprotected by the processes taught herein. Preferably, such a protectiveoverlying metallization layer would be formed where there is anincreased likelihood that subsequent etch steps may lose selectivity orwhere an error in mask formation would otherwise allow damage tounderlying semiconductor device features.

Though the present invention has been described herein with reference tospecific examples, such examples are for illustrative purposes only. Thescope of the present invention is defined by the appended claims and is,therefore, not limited by the preceding description or the referenceddrawings.

What is claimed is:
 1. A method of forming a stacked local interconnectin a semiconductor substrate having a plurality of electrical featuresformed thereon, at least one electrical feature of said plurality beingan electrical contact located on a surface of said semiconductorsubstrate, having at least one etch stop layer on at least a portion ofsaid surface of said semiconductor substrate, and having a passivationlayer covering at least a portion of said at least one etch stop layerand covering at least a portion of said electrical contact, said methodcomprising: forming a first local interconnect; depositing a layer ofresist over at least a portion of said at least one etch stop layer;patterning said layer of resist; providing a self-aligned contactetching process; etching through at least a portion of said passivationlayer using said self-aligned contact etching process; exposing aportion of said electrical contact using said etching through said atleast a portion of said passivation layer; forming a second localinterconnect electrically connecting a first group of electricalfeatures included within said plurality of electrical features;electrically connecting said second local interconnect to said firstlocal interconnect during said forming thereof; and forming a thirdlocal interconnect electrically connected to said first localinterconnect and at least one electrical feature of said plurality ofelectrical features.
 2. The method according to claim 1, wherein said atleast one etch stop layer comprises a layer of SiO₂ over at least aportion of said surface of said semiconductor substrate.
 3. The methodaccording to claim 1, wherein said passivation layer covering at least aportion of said at least one etch stop layer comprises a passivationlayer including a silicate material selected from a group consisting ofBPSG, PSG, and BSG.
 4. The method according to claim 1, furthercomprising providing an interlayer dielectric over said passivationlayer.
 5. The method according to claim 4, wherein providing saidinterlayer dielectric over said passivation layer comprises providing alayer of dielectric material selected from a group consisting of SiO₂,Si_(x)O_(y)N₂, TEOS, and Si₃N₄.
 6. The method of claim 4, whereinforming said first local interconnect comprises: forming a resist layerover said interlayer dielectric; exposing and developing said resistlayer to define a pattern in said resist layer exposing a portion ofsaid interlayer dielectric, said pattern corresponding in size, shape,and location to said first local interconnect; forming a trench byetching said exposed portion of said interlayer dielectric; and fillingsaid trench with a conductive material.
 7. The method of claim 6,wherein filling said trench with said conductive material comprises:forming a layer of conductive material over said trench and saidinterlayer dielectric; and polishing said layer of conductive materialto form said first local interconnect, said first local interconnecthaving a top surface which is substantially coplanar with a top surfaceof said interlayer dielectric.
 8. The method of claim 6, wherein fillingsaid trench with said conductive material comprises: forming a barrierlayer over said trench and said interlayer dielectric, said barrierlayer partially filling said trench; forming a layer of conductivematerial over said barrier layer; and polishing said barrier layer andsaid layer of conductive material to form said first local interconnect,said first local interconnect having a top surface which issubstantially coplanar with a top surface of said interlayer dielectric.9. The method of claim 6, wherein forming said second local interconnectand forming said third local interconnect comprise: forming a secondresist layer; exposing and developing said second resist layer to definea pattern in said second resist layer exposing portions of saidinterlayer dielectric, said pattern in said second resist includingareas corresponding in size, shape and location to said second and thirdlocal interconnects; etching said interlayer dielectric and saidpassivation layer to create openings revealing electrical features to beelectrically connected by said second local interconnect and said thirdlocal interconnect; removing portions of said at least one etch stoplayer overlying said electrical features to be electrically connected;and filling said openings with conductive material.
 10. The method ofclaim 9, wherein filling said openings with said conductive materialcomprises: forming a layer of conductive material over said openings andsaid interlayer dielectric; and polishing said layer of conductivematerial to form said second local interconnect and said third localinterconnect, said second local interconnect and said third localinterconnect each having a top surface which is substantially coplanarwith a top surface of said interlayer dielectric.
 11. The method ofclaim 9, wherein filling said openings with said conductive materialcomprises: forming a barrier layer over said openings and saidinterlayer dielectric, said barrier layer partially filling saidopenings; forming a layer of conductive material over said barrierlayer; and polishing said barrier layer and said layer of conductivematerial to form said second local interconnect and said third localinterconnect, said second local interconnect and said third localinterconnect each having a top surface which is substantially coplanarwith a top surface of said interlayer dielectric.
 12. A method offorming a stacked local interconnect in a semiconductor substrate havinga plurality of electrical features formed thereon, at least oneelectrical feature of said plurality being an electrical contact locatedon a surface of said semiconductor substrate, having at least one etchstop layer on at least a portion of said surface of said semiconductorsubstrate, and having a passivation layer covering at least a portion ofsaid at least one etch stop layer and covering at least a portion ofsaid electrical contact, said method comprising: forming a first portionof said stacked local interconnect; depositing a layer of resist over atleast a portion of said at least one etch stop layer; patterning saidlayer of resist; providing a self-aligned contact etching process;etching through at least a portion of said passivation layer using saidself-aligned contact etching process; exposing a portion of saidelectrical contact during said etching through said at least a portionof said passivation layer; forming a second portion of said stackedlocal interconnect; electrically connecting a portion of said secondportion of said stacked local interconnect to a first electrical featureincluded within said plurality of electrical features to said firstportion of said stacked local interconnect; and forming a third portionof said stacked local interconnect, said third portion electricallyconnecting a second electrical feature included within said plurality ofelectrical features to said first portion of said stacked localinterconnect.
 13. The method according to claim 12, further comprisingproviding an interlayer dielectric over said passivation layer.
 14. Themethod of claim 13, wherein forming said first portion of said stackedlocal interconnect comprises: forming a resist layer over saidinterlayer dielectric; exposing and developing said resist layer todefine a pattern in said resist layer exposing a portion of saidinterlayer dielectric, said pattern corresponding in size, shape, andlocation to said first portion of said stacked local interconnect; andforming a trench by etching said exposed portion of said interlayerdielectric; and filling said trench with a conductive material.
 15. Themethod of claim 13, wherein forming said second portion of said stackedlocal interconnect and said third portion of said stacked localinterconnect comprises: forming a second resist layer; exposing anddeveloping said second resist layer to define a pattern in said secondresist layer exposing portions of said interlayer dielectric, saidpattern including areas corresponding in size, shape and location tosaid second portion of said stacked local interconnect and said thirdportion of said stacked local interconnect; etching said interlayerdielectric and said passivation layer to create openings revealingelectrical features to be electrically connected to said first portionof said stacked local interconnect; removing portions of said at leastone etch stop layer overlying said electrical features to beelectrically connected to said first portion of said stacked localinterconnect; and filling said openings with conductive material.